module bcdcounter (
    clk, en, r, q, co
);

  parameter modulus = 8'h63;

  input clk, en, r;
  output co;
  output [7:0] q;
  reg [7:0] q;

  assign co = (q==modulus) && en;

  always @(posedge clk) begin
    if ( r )  q = 8'h00;
    else if ( en ) begin
      if ( q==modulus )  q = 0;
      else if ( q[3:0] == 9 ) begin
        q[3:0] = 0;
        q[7:4] = q[7:4] + 1;
        end
      else
        q[3:0] = q[3:0] + 1;
    end
  end
endmodule